Frequency Synthesizers

When you set a signal generator to 14.200000 MHz, select a channel on a two-way radio, or a Wi-Fi chip hops to a new channel, the new frequency appears exactly, perfectly stable from the moment it is selected — that is a frequency synthesizer at work. Before synthesizers became practical in the 1970s, radios and signal generators either used crystals (one crystal per frequency, a limited number of channels) or variable-frequency oscillators (continuous tuning, but prone to drift). The synthesizer ended both limitations at once: it delivers the stability of a crystal oscillator and the flexibility of a VFO, with the ability to tune to any frequency in a wide range in precise steps.

A frequency synthesizer is essentially a PLL-based circuit that translates a single stable reference frequency into any desired output frequency by controlling the parameters of the feedback loop. Understanding how this translation works — and the compromises involved — is essential for anyone who wants to understand how modern radios, wireless chips, processors and signal generators function.

Why Frequency Synthesis Was Revolutionary

Consider the situation facing a radio or test-equipment designer in 1960 who wanted equipment to cover a range of frequencies accurately. The options were:

Crystal-controlled: Use a separate crystal for each frequency. Two-way radios, aircraft radios and early channelized equipment did exactly this, with a crystal (or two) for every channel. Crystals cost money, each one had to be ordered for its exact frequency, and the equipment could only operate on pre-selected frequencies.

VFO-controlled: Use a single LC oscillator, tunable across the whole range. This gave full frequency agility but required extreme mechanical and thermal stability to prevent drift. Warm-up drift, microphonics, supply sensitivity and component aging all required constant countermeasures, and the frequency dial was only as accurate as its calibration.

The frequency synthesizer resolved both problems. By locking a VCO to a crystal reference through a programmable PLL, engineers achieved the frequency agility of a VFO with stability approaching that of a crystal oscillator. Modern synthesizers tune in steps as fine as 1 Hz or less, and every step is crystal-accurate — typically ±1 ppm or better across the entire range, essentially the accuracy of the reference crystal.

Integer-N Synthesis: The Foundation

Integer-N synthesizer architecture. The reference crystal is divided by R to set the comparison frequency (channel spacing). The VCO output is divided by programmable integer N and compared against the reference at the phase detector. When locked, f_VCO = N × (f_ref/R).

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The integer-N synthesizer is the direct application of the PLL principle described in the previous lesson, extended with a reference divider to make the channel spacing practical. It has two programmable dividers:

The R divider (reference divider) divides the crystal reference frequency down to the desired channel spacing frequency. If your crystal runs at 5.000 MHz and you want 5 kHz channel spacing, R = 5,000,000 / 5,000 = 1,000. The phase detector sees 5 kHz on both inputs when locked.

The N divider (feedback divider) divides the VCO output down to the same channel spacing frequency before feeding it back to the phase detector. When locked:

To tune to a different frequency, you change N. The PLL acquires lock at the new frequency, which takes from a few hundred microseconds to several milliseconds depending on the loop bandwidth. A microcontroller can reprogram a synthesizer IC's N register over SPI or I²C in microseconds, making frequency changes nearly instantaneous from the user's point of view.

Channel Spacing and Reference Frequency

The relationship between reference frequency and channel spacing is fixed by the integer-N architecture. The phase detector comparison frequency equals the channel spacing — and this creates a fundamental trade-off. Finer channel spacing requires a lower comparison frequency, which means:

• The N divider becomes larger (for HF synthesis with 1 Hz steps, N can be in the millions)
• The loop bandwidth must be kept narrow relative to the comparison frequency (typically loop bandwidth ≤ comparison frequency / 10 to prevent instability)
• A narrower loop bandwidth means slower lock time and less VCO noise suppression
• Reference spurs at the comparison frequency are closer to the carrier and harder to filter

This is why early PLL synthesizers typically offered 5 kHz to 25 kHz channel spacing — fine enough for channelized AM and FM radio, but too coarse for signal generators and receivers that need to tune in 100 Hz or even 1 Hz steps. Fine-step synthesis required either fractional-N techniques (developed in the 1980s) or offset techniques (discussed below).

The Frequency Offset Trick

Many designs solved the channel spacing problem by combining a coarse synthesizer with a fine-tuning oscillator. The synthesizer provides the main frequency in, say, 10 kHz steps. A separate VFO (analog or digital) covers a span of ±10 kHz with fine, continuous resolution. The two outputs are mixed to produce any frequency within the range. This approach appears in many receivers, transmitters and signal generators of the 1970s and 1980s.

Prescalers and Dual-Modulus Division

At RF frequencies (say, 144 MHz), the N divider must count at 144 MHz / N_value per cycle. CMOS logic at that era could not count fast enough to directly implement a programmable N divider at UHF or microwave frequencies. The solution is a prescaler: a fast fixed-ratio divider (implemented in ECL or BiCMOS) that first divides the VCO output by a fixed number P to bring it down to a frequency manageable by slower logic. The slower programmable counter then divides by A or B, and the combination gives an effective divide ratio.

Dual-Modulus Prescaler

A dual-modulus prescaler can switch between two division ratios on command — typically P and P+1. Suppose P = 10. The prescaler normally divides by 10, but when commanded, it divides by 11. By combining this with two counters (an A counter and a B counter), the overall divide ratio N can be set to any integer from P (B−A) to P×B + A, covering all integers above a certain minimum. This makes a fully programmable synthesizer at high frequencies possible with only one fast divider stage.

The principle: count B cycles with the prescaler at ÷P/÷(P+1) mode. For the first A counts, use ÷(P+1). For the remaining B−A counts, use ÷P. Total counts at VCO frequency = A×(P+1) + (B−A)×P = AP + A + BP − AP = BP + A. So N = BP + A. With P = 8, A and B programmable independently, every integer N above 8 is achievable.

Modern synthesizer ICs have integrated the prescaler, A and B counters, and even the phase detector and charge pump into a single chip. The ADF4350 from Analog Devices, for example, covers 137.5 MHz to 4.4 GHz with a programmable divider and fractional-N capability, all in a 24-pin package.

Worked Example: 2-Meter FM Synthesizer

Fractional-N Synthesis: Finer Resolution

The integer-N architecture is limited: the channel spacing equals the comparison frequency, which means a 1 kHz comparison frequency is needed for 1 kHz steps. With a 1 kHz comparison frequency, N can be over 14,000 for HF, the loop bandwidth is forced below 100 Hz, reference spurs are very close to the carrier, and the PLL responds extremely slowly.

Fractional-N synthesis breaks the integer-N constraint by allowing the effective divide ratio to be a fraction. If the divider alternates between N and N+1 in a controlled pattern, the average divide ratio is N + k/M for some integers k and M. The output frequency is then:

Delta-Sigma Modulation and Noise Shaping

The simple fractional-N approach described above has a problem: the alternation between N and N+1 creates periodic phase disturbances at the phase detector at the fractional frequency. These appear as spurs on the output at offsets equal to the fractional frequency × comparison frequency. With k/M = 0.575, the pattern repeats with period 1/0.575 of the comparison frequency, producing a spur at about 5.75 kHz offset — potentially right in the receiver's passband.

The solution is delta-sigma modulation of the divide ratio. Instead of a simple periodic pattern, the delta-sigma modulator uses a feedback accumulator to create a pseudorandom sequence of divide ratios that achieves the correct average but whose spectral content is pushed to high frequencies (noise-shaped away from the carrier). The loop filter then suppresses this high-frequency noise.

A high-order delta-sigma modulator (third or fourth order) can shape virtually all the fractional noise above the loop bandwidth, leaving the output spectrum clean except for very close-in noise. This is why modern fractional-N synthesizers achieve low spurious outputs despite varying the divide ratio thousands of times per second. All modern synthesizer ICs — ADF4350/ADF4351 from Analog Devices, LMX2595 from Texas Instruments, Si4133 from Silicon Labs — use sigma-delta fractional-N architecture.

Synthesizer ICs: From Discrete to Integrated

The evolution from discrete PLL components to integrated synthesizer chips has been dramatic. In the late 1970s, building a PLL synthesizer required a handful of TTL or CMOS logic chips for the dividers, a separate PFD chip, a discrete charge pump, a loop filter, and a separate VCO. Today, a single small IC can provide the reference divider, PFD, charge pump, all programmable dividers, and even the VCO in one package.

The Si5351A deserves special mention. At under $3 in single quantities and using a simple I²C interface that any microcontroller (including an Arduino) can drive, it has become the go-to synthesizer IC for hobby projects. It provides three independent fractional-N synthesized outputs anywhere from below 1 MHz to 200 MHz — enough for a receiver's local oscillators, a clock generator, or a simple signal source, all from one chip. It is designed as a clock generator, so its outputs are square waves that need filtering where a sine wave is required.

Key Synthesizer Specifications

Synthesizers in a Complete Radio

A typical modern radio receiver or transmitter contains several synthesized signal sources working together, all derived from one reference crystal. Understanding where each lives gives you a complete picture of the signal flow.

The Local Oscillator Synthesizer

The main synthesizer generates the local oscillator frequency that drives the first mixer in the receiver (and the exciter in a transmitter). Retuning the radio means reprogramming the N value in this synthesizer. With an IF of, say, 9 MHz, receiving on 14.200 MHz requires an LO at 14.200 + 9 = 23.200 MHz (high-side injection) or 14.200 − 9 = 5.200 MHz (low-side injection).

The Demodulator Oscillator

To demodulate single-sideband and data signals, a second synthesized frequency is injected at the product detector after the IF filter. Its frequency is set to the IF plus or minus the required audio offset, and it must be programmable because different signal types need it on different sides of the carrier.

The Reference and Calibration

Every synthesized frequency inherits the accuracy of the reference oscillator, typically a 10 MHz or 26 MHz TCXO. Many instruments and radios provide a reference input so that they can be locked to an external standard, such as a GPS-disciplined oscillator, or a calibration signal that can be compared against a time-and-frequency broadcast station.

Multi-Loop Synthesizers

High-performance signal generators and receivers use multiple PLL loops to achieve both fine resolution and very low phase noise at the same time. A common approach is the two-loop synthesizer: one loop produces a low-noise coarse frequency with a high comparison frequency; a second produces a fine offset; the two are mixed to give the final output with the resolution of the second loop and the phase noise of the first. Wireless chips and many modern instruments achieve similar results with a single fractional-N loop and a very clean reference.